The functional parameters of any ESD protection snapback structure, such as a GGNMOS, LVTSCR, NPN-BJT has to fit within a so-called ESD protection window. The triggering voltage of the ESD structure has to be lower than the primary breakdown voltage of the device(s) it is protecting, but it has to have a holding voltage that exceeds the normal operating voltage of the protected devices, to avoid latch-up. However, the internal circuit that is being protected typically has a similar breakdown voltage as the ESD structure, and often tends to breakdown before the triggering voltage of the ESD protection structure is reached. The backend resistance further exacerbates this problem since it provides an additional voltage drop, thereby exposing the internal circuit to an increased voltage comprising the breakdown voltage plus the additional voltage drop across the backend resistance.
Some attempts at resolving this problem include using different dynamic driver circuits to help in triggering the ESD structure. This is not always suitable because the electrode for realizing such a dynamic driver circuit may be missing, or space constraints may make the additional circuitry undesirable. Another approach involves the use of ESD implants to reduce the triggering voltage by reducing the number of carriers that are diverted into the substrate. However this requires additional process steps, making the solution more expensive to implement.
It is also desirable that a solution involve typical process steps and avoid any additional process steps.